Tamarin: tamarin-central/codegen/ArmAssembler.h Source File

00001 /* ***** BEGIN LICENSE BLOCK *****
00002  * Version: MPL 1.1/GPL 2.0/LGPL 2.1
00003  *
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00009  * Software distributed under the License is distributed on an "AS IS" basis,
00010  * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
00011  * for the specific language governing rights and limitations under the
00012  * License.
00013  *
00014  * The Original Code is [Open Source Virtual Machine.].
00015  *
00016  * The Initial Developer of the Original Code is
00017  * Adobe System Incorporated.
00018  * Portions created by the Initial Developer are Copyright (C) 2004-2006
00019  * the Initial Developer. All Rights Reserved.
00020  *
00021  * Contributor(s):
00022  *   Adobe AS3 Team
00023  *
00024  * Alternatively, the contents of this file may be used under the terms of
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00036  * ***** END LICENSE BLOCK ***** */
00037 
00038 #ifndef __avmplus_ArmAssembler__
00039 #define __avmplus_ArmAssembler__
00040 
00041 
00042 namespace avmplus
00043 {
00044     class ArmAssembler
00045     {
00046     public:
00047         /* ARM registers */
00048         typedef enum 
00049         {
00050             R0  = 0,
00051             R1  = 1,
00052             R2  = 2,
00053             R3  = 3,
00054             R4  = 4,
00055             R5  = 5,
00056             R6  = 6,
00057             R7  = 7,
00058             R8  = 8,
00059             R9  = 9,
00060             R10 = 10,
00061             FP  = 11,
00062             IP  = 12,
00063             SP  = 13,
00064             LR  = 14,
00065             PC  = 15,
00066 
00067             // Pseudo-register for floating point
00068             F0  = 0,
00069             
00070             Unknown = -1
00071         }
00072         Register;
00073 
00074         /* ARM registers */
00075         typedef enum 
00076         {
00077             R0_mask  = (1<<0),
00078             R1_mask  = (1<<1),
00079             R2_mask  = (1<<2),
00080             R3_mask  = (1<<3),
00081             R4_mask  = (1<<4),
00082             R5_mask  = (1<<5),
00083             R6_mask  = (1<<6),
00084             R7_mask  = (1<<7),
00085             R8_mask  = (1<<8),
00086             R9_mask  = (1<<9),
00087             R10_mask = (1<<10),
00088             FP_mask  = (1<<11),
00089             IP_mask  = (1<<12),
00090             SP_mask  = (1<<13),
00091             LR_mask  = (1<<14),
00092             PC_mask  = (1<<15)
00093         }
00094         RegisterMask;
00095         
00096         /* ARM condition codes */
00097         typedef enum
00098         {
00099             EQ = 0x0, // Equal
00100             NE = 0x1, // Not Equal
00101             CS = 0x2, // Carry Set (or HS)
00102             CC = 0x3, // Carry Clear (or LO)
00103             MI = 0x4, // MInus
00104             PL = 0x5, // PLus
00105             VS = 0x6, // oVerflow Set
00106             VC = 0x7, // oVerflow Clear
00107             HI = 0x8, // HIgher
00108             LS = 0x9, // Lower or Same
00109             GE = 0xA, // Greater or Equal
00110             LT = 0xB, // Less Than
00111             GT = 0xC, // Greater Than
00112             LE = 0xD, // Less or Equal
00113             AL = 0xE, // ALways
00114             NV = 0xF  // NeVer
00115         }
00116         ConditionCode;
00117 
00118         /* --- Data Processing Instructions --- */
00119 
00120         /* Values for operator "a" */
00121         typedef enum
00122         {
00123             AND_op = 0x0, // Boolean And                 Rd = Rn AND Op2
00124             EOR_op = 0x1, // Boolean Eor                 Rd = Rn EOR Op2
00125             SUB_op = 0x2, // Subtract                    Rd = Rn - Op2
00126             RSB_op = 0x3, // Reverse Subtract            Rd = Op2 - Rn
00127             ADD_op = 0x4, // Addition                    Rd = Rn + Op2
00128             ADC_op = 0x5, // Add with Carry              Rd = Rn + Op2 + C
00129             SBC_op = 0x6, // Subtract with Carry         Rd = Rn - Op2 - (1-C)
00130             RSC_op = 0x7, // Reverse Subtract with Carry Rd - Op2 - Rn - (1-C)
00131             TST_op = 0x8, // Test bit                    Rn AND Op2
00132             TEQ_op = 0x9, // Test equality               Rn EOR Op2
00133             CMP_op = 0xA, // Compare                     Rn - Op2
00134             CMN_op = 0xB, // Compare Negative            Rn + Op2
00135             ORR_op = 0xC, // Boolean Or                  Rd = Rn OR Op2
00136             MOV_op = 0xD, // Move value                  Rd = Op2
00137             BIC_op = 0xE, // Bit Clear                   Rd = Rn AND NOT Op2
00138             MVN_op = 0xF  // Move Not                    Rd = NOT Op2
00139         }
00140         Operator;
00141 
00142         /* Values for operand "t" */
00143         typedef enum
00144         {
00145             LSL_imm = 0, // LSL #c - Logical Shift Left
00146             LSL_reg = 1, // LSL Rc - Logical Shift Left
00147             LSR_imm = 2, // LSR #c - Logical Shift Right
00148             LSR_reg = 3, // LSR Rc - Logical Shift Right
00149             ASR_imm = 4, // ASR #c - Arithmetic Shift Right
00150             ASR_reg = 5, // ASR Rc - Arithmetic Shift Right
00151             ROR_imm = 6, // Rotate Right (c != 0)
00152             RRX     = 6, // Rotate Right one bit with extend (c == 0)
00153             ROR_reg = 7  // Rotate Right
00154         }
00155         ShiftOperator;
00156 
00157         typedef uint32 MDInstruction;
00158         
00159         /* Instruction pointer */
00160         MDInstruction *mip;
00161         MDInstruction *mipStart;
00162 
00163         int     mInstructionCount;  // number of machine instructions
00164 
00165         /* Current condition code */
00166         ConditionCode conditionCode;
00167 
00168         ArmAssembler();
00169         
00170         void SET_CONDITION_CODE(ConditionCode conditionCode);
00171         
00172         void IMM32(int value);
00173         void MOV(Register dst, Register src);
00174         void STMFD_bang(Register dst, int mask);
00175         void SUB_imm8(Register dst, Register src, int imm8);
00176         void RSB_imm8(Register dst, Register src, int imm8);
00177         void B(int offset24);       
00178         void BL(int offset24);
00179         void LDR(Register dst, int offset, Register base);
00180         void BIC_imm8(Register dst, Register src, int imm8);
00181         void MOV_imm8(Register dst, int imm8);
00182         void MOV_imm16(Register dst, int imm16);
00183         void CMP_imm8(Register src, int imm8);
00184         void ADD(Register dst, Register src1, Register src2);
00185         void SUB(Register dst, Register src1, Register src2);
00186         void AND(Register dst, Register src1, Register src2);
00187         void ORR(Register dst, Register src1, Register src2);
00188         void EOR(Register dst, Register src1, Register src2);
00189         void MUL(Register dst, Register src1, Register src2);
00190         void CMP(Register Rn, Register Rm);     
00191         void LSL(Register dst, Register src, Register rShift);
00192         void LSR(Register dst, Register src, Register rShift);
00193         void ASR(Register dst, Register src, Register rShift);
00194         void LSL_i(Register dst, Register src, int iShift);
00195         void LSR_i(Register dst, Register src, int iShift);
00196         void ASR_i(Register dst, Register src, int iShift);
00197         void STR(Register src, int offset, Register base);
00198         void ADD_imm8(Register dst, Register src, int imm8);
00199         void ADD_imm8_hi(Register dst, Register src, int imm8);
00200         void ADD_imm16(Register dst, Register src, int imm16);
00201         void AND_imm8(Register dst, Register src, int imm8);
00202         void ORR_imm8(Register dst, Register src, int imm8);
00203         void EOR_imm8(Register dst, Register src, int imm8);
00204         void LDMFD(Register src, int mask);
00205         void LDMFD_bang(Register src, int mask);        
00206 
00207         // Cheeseball way of doing imm32.
00208         void MOV_imm32(Register dst, int imm32);
00209 
00210         void flushDataCache(void *start, int len);
00211         
00212         // Set if verbose output desired
00213         #ifdef AVMPLUS_VERBOSE
00214         bool verboseFlag;
00215         #endif
00216         PrintWriter *console;
00217 
00218         // Immediate pool
00219         MDInstruction *immediatePool;
00220         int immediatePoolCount;
00221         const static int kImmediatePoolMax = 16;
00222         
00223         static const char* const regNames[];
00224 #define gpregNames regNames
00225         static const char* const conditionCodes[];
00226     };
00227 }
00228 
00229 #endif /* __avmplus_ArmAssembler__ */