nanojit Namespace Reference


Classes

struct  GuardRecord
struct  SideExit
struct  Reservation
struct  AR
struct  Stats
class  MMGC_SUBCLASS_DECL
class  LabelStateMap
struct  PageHeader
struct  Page
class  BlockHist
class  Fragmento
class  Fragment
struct  CallInfo
class  LIns
class  LirWriter
class  ExprFilter
class  LInsHashSet
class  CseFilter
class  LirBuffer
class  LirBufWriter
class  LirFilter
class  LirReader
class  StackFilter
class  CseReader
class  LoadFilter
struct  _FragInfo

Typedefs

typedef avmplus::List< NIns *,
avmplus::LIST_NonGCObjects > 		NInsList
typedef avmplus::SortedMap<
LIns *, NIns *, avmplus::LIST_NonGCObjects > 		InsMap
typedef avmplus::SortedMap<
NIns *, LIns *, avmplus::LIST_NonGCObjects > 		NInsMap
typedef avmplus::List< Page *,
avmplus::LIST_NonGCObjects > 		AllocList
typedef avmplus::GCSortedMap<
const void *, uint32_t, avmplus::LIST_NonGCObjects > 		BlockSortedMap
typedef LIns * LInsp
typedef uint8_t NIns
typedef int RegisterMask
typedef int NIns
typedef int RegisterMask
typedef nanojit::_FragInfo FragInfo
typedef uint8_t NIns
typedef int RegisterMask
typedef unsigned short NIns
typedef int RegisterMask
typedef nanojit::_FragInfo FragInfo

Enumerations

enum  AssmError {
  None = 0, OutOMem, StackFull, ResvFull,
  RegionFull, MaxLength, MaxExit, MaxXJump,
  UnknownPrim, UnknownBranch
}
enum  TraceKind { LoopTrace, BranchTrace, MergeTrace }
enum  LOpcode {
  LIR64 = 0x40, LIR_start = 0, LIR_nearskip = 1, LIR_skip = 2,
  LIR_neartramp = 3, LIR_tramp = 4, LIR_addp = 9, LIR_param = 10,
  LIR_st = 11, LIR_ld = 12, LIR_alloc = 13, LIR_sti = 14,
  LIR_ret = 15, LIR_live = 16, LIR_calli = 17, LIR_call = 18,
  LIR_loop = 19, LIR_x = 20, LIR_j = 21, LIR_jt = 22,
  LIR_jf = 23, LIR_label = 24, LIR_ji = 25, LIR_feq = 26,
  LIR_flt = 27, LIR_fgt = 28, LIR_fle = 29, LIR_fge = 30,
  LIR_cmov = 31, LIR_short = 32, LIR_int = 33, LIR_ldc = 34,
  LIR_2 = 35, LIR_neg = 36, LIR_add = 37, LIR_sub = 38,
  LIR_mul = 39, LIR_callh = 40, LIR_and = 41, LIR_or = 42,
  LIR_xor = 43, LIR_not = 44, LIR_lsh = 45, LIR_rsh = 46,
  LIR_ush = 47, LIR_xt = 48, LIR_xf = 49, LIR_qlo = 50,
  LIR_qhi = 51, LIR_ldcb = 52, LIR_ov = 53, LIR_cs = 54,
  LIR_eq = 55, LIR_lt = 56, LIR_gt = 57, LIR_le = 58,
  LIR_ge = 59, LIR_ult = 60, LIR_ugt = 61, LIR_ule = 62,
  LIR_uge = 63, LIR_file = 1 | LIR64, LIR_line = 2 | LIR64, LIR_stq = LIR_st | LIR64,
  LIR_stqi = LIR_sti | LIR64, LIR_fret = LIR_ret | LIR64, LIR_quad = LIR_int | LIR64, LIR_ldq = LIR_ld | LIR64,
  LIR_ldqc = LIR_ldc | LIR64, LIR_fcall = LIR_call | LIR64, LIR_fcalli = LIR_calli | LIR64, LIR_fneg = LIR_neg | LIR64,
  LIR_fadd = LIR_add | LIR64, LIR_fsub = LIR_sub | LIR64, LIR_fmul = LIR_mul | LIR64, LIR_fdiv = 40 | LIR64,
  LIR_qjoin = 41 | LIR64, LIR_i2f = 42 | LIR64, LIR_u2f = 43 | LIR64
}
enum  AbiKind { ABI_FASTCALL, ABI_THISCALL, ABI_STDCALL, ABI_CDECL }
enum  ArgSize {
  ARGSIZE_NONE = 0, ARGSIZE_F = 1, ARGSIZE_LO = 2, ARGSIZE_Q = 3,
  _ARGSIZE_MASK_INT = 2, _ARGSIZE_MASK_ANY = 3
}
enum  Register {
  RAX = 0, RCX = 1, RDX = 2, RBX = 3,
  RSP = 4, RBP = 5, RSI = 6, RDI = 7,
  SP = RSP, SP = 13, SP = ESP, SP = 13,
  FP = RBP, FP = 13, FP = EBP, FP = SP,
  R8 = 8, R8 = 8, R8 = 8, R9 = 9,
  R9 = 9, R10 = 10, R10 = 10, R11 = 11,
  R12 = 12, R13 = 13, R14 = 14, R15 = 15,
  XMM0 = 16, XMM0 = 8, XMM1 = 17, XMM1 = 9,
  XMM2 = 18, XMM2 = 10, XMM3 = 19, XMM3 = 11,
  XMM4 = 20, XMM4 = 12, XMM5 = 21, XMM5 = 13,
  XMM6 = 22, XMM6 = 14, XMM7 = 23, XMM7 = 15,
  XMM8 = 24, XMM9 = 25, XMM10 = 26, XMM11 = 27,
  XMM12 = 28, XMM13 = 29, XMM14 = 30, XMM15 = 31,
  FirstReg = 0, FirstReg = 0, FirstReg = 0, FirstReg = 0,
  LastReg = 31, LastReg = 10, LastReg = 23, LastReg = 5,
  UnknownReg = 32, UnknownReg = 11, UnknownReg = 24, UnknownReg = 6
}
enum  Register {
  R0 = 0, R0 = 0, R1 = 1, R1 = 1,
  R2 = 2, R2 = 2, R3 = 3, R3 = 3,
  R4 = 4, R4 = 4, R5 = 5, R5 = 5,
  R6 = 6, R6 = 6, R7 = 7, R7 = 7,
  R8 = 8, R8 = 8, R8 = 8, R9 = 9,
  R9 = 9, R10 = 10, R10 = 10, IP = 12,
  IP = 12, SP = RSP, SP = 13, SP = ESP,
  SP = 13, LR = 14, LR = 14, PC = 15,
  PC = 15, FP = RBP, FP = 13, FP = EBP,
  FP = SP, F0 = 0, FRAME_PTR = 11, FRAME_PTR = R7,
  ESP = 13, ESP = 4, FirstReg = 0, FirstReg = 0,
  FirstReg = 0, FirstReg = 0, LastReg = 31, LastReg = 10,
  LastReg = 23, LastReg = 5, Scratch = 12, Scratch = 6,
  UnknownReg = 32, UnknownReg = 11, UnknownReg = 24, UnknownReg = 6
}
enum  ConditionCode {
  EQ = 0x0, NE = 0x1, CS = 0x2, CC = 0x3,
  MI = 0x4, PL = 0x5, VS = 0x6, VC = 0x7,
  HI = 0x8, LS = 0x9, GE = 0xA, LT = 0xB,
  GT = 0xC, LE = 0xD, AL = 0xE, NV = 0xF
}
enum  Register {
  EAX = 0, ECX = 1, EDX = 2, EBX = 3,
  ESP = 13, ESP = 4, EBP = 5, ESI = 6,
  EDI = 7, SP = RSP, SP = 13, SP = ESP,
  SP = 13, FP = RBP, FP = 13, FP = EBP,
  FP = SP, XMM0 = 16, XMM0 = 8, XMM1 = 17,
  XMM1 = 9, XMM2 = 18, XMM2 = 10, XMM3 = 19,
  XMM3 = 11, XMM4 = 20, XMM4 = 12, XMM5 = 21,
  XMM5 = 13, XMM6 = 22, XMM6 = 14, XMM7 = 23,
  XMM7 = 15, FST0 = 16, FST1 = 17, FST2 = 18,
  FST3 = 19, FST4 = 20, FST5 = 21, FST6 = 22,
  FST7 = 23, FirstReg = 0, FirstReg = 0, FirstReg = 0,
  FirstReg = 0, LastReg = 31, LastReg = 10, LastReg = 23,
  LastReg = 5, UnknownReg = 32, UnknownReg = 11, UnknownReg = 24,
  UnknownReg = 6
}
enum  Register {
  R0 = 0, R0 = 0, R1 = 1, R1 = 1,
  R2 = 2, R2 = 2, R3 = 3, R3 = 3,
  R4 = 4, R4 = 4, R5 = 5, R5 = 5,
  R6 = 6, R6 = 6, R7 = 7, R7 = 7,
  R8 = 8, R8 = 8, R8 = 8, IP = 12,
  IP = 12, SP = RSP, SP = 13, SP = ESP,
  SP = 13, LR = 14, LR = 14, PC = 15,
  PC = 15, FP = RBP, FP = 13, FP = EBP,
  FP = SP, FRAME_PTR = 11, FRAME_PTR = R7, FirstReg = 0,
  FirstReg = 0, FirstReg = 0, FirstReg = 0, LastReg = 31,
  LastReg = 10, LastReg = 23, LastReg = 5, Scratch = 12,
  Scratch = 6, UnknownReg = 32, UnknownReg = 11, UnknownReg = 24,
  UnknownReg = 6
}

Functions

int32_t disp (Reservation *r)
uint32_t argwords (uint32_t argc)
bool isGuard (LOpcode op)
bool isCall (LOpcode op)
bool isStore (LOpcode op)
bool isConst (LOpcode op)
bool isLoad (LOpcode op)
bool FASTCALL isCse (LOpcode v)
bool FASTCALL isCmp (LOpcode v)
bool FASTCALL isCond (LOpcode v)
bool isRet (LOpcode c)
bool FASTCALL isFloat (LOpcode v)
LIns *FASTCALL callArgN (LInsp i, uint32_t n)
void compile (Assembler *assm, Fragment *frag)
 verbose_only (void printTracker(const char *s, avmplus::RegionTracker &trk, Assembler *assm);) verbose_only(void live(GC *gc
 verbose_only (extern const char *regNames[];) typedef enum
RegisterMask rmask (Register r)

Variables

const uint8_t operandCount []
LirBuffer * lirbuf
const uint32_t NJ_PAGE_SIZE = 1 << NJ_LOG2_PAGE_SIZE
const int NJ_LOG2_PAGE_SIZE = 12
const int NJ_MAX_REGISTERS = 32
const int NJ_STACK_OFFSET = 0
const bool NJ_UNLIMITED_GROWTH = true
const int NJ_ALIGN_STACK = 16
static const RegisterMask SavedRegs = (1<<R13) | (1<<R14) | (1<<R15)
static const RegisterMask TempRegs = (1<<RAX) | (1<<RCX) | (1<<RDX) | (1<<R8) | (1<<R9) | (1<<R10) | (1<<R11) | (1<<RDI) | (1<<RSI)
static const RegisterMask GpRegs = SavedRegs | TempRegs
static const RegisterMask XmmRegs = (1<<XMM0) | (1<<XMM1) | (1<<XMM2) | (1<<XMM3) | (1<<XMM4) | (1<<XMM5) | (1<<XMM6) | (1<<XMM7) | (1<<XMM8) | (1<<XMM9) | (1<<XMM10) | (1<<XMM11) | (1<<XMM13) | (1<<XMM14) | (1<<XMM15)
static const RegisterMask FpRegs = XmmRegs
static const RegisterMask ScratchRegs = TempRegs | XmmRegs
static const RegisterMask AllowableFlagRegs = GpRegs
const int NJ_LOG2_PAGE_SIZE = 12
const int NJ_MAX_CPOOL_OFFSET = 4096
const int NJ_CPOOL_SIZE = 16
static const RegisterMask SavedRegs = 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10
static const RegisterMask FpRegs = 0x0000
static const RegisterMask GpRegs = 0x07FF
static const RegisterMask AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10
 ShiftOperator
const int NJ_LOG2_PAGE_SIZE = 12
const int NJ_MAX_REGISTERS = 24
const int NJ_STACK_OFFSET = 0
const int NJ_ALIGN_STACK = 16
static const RegisterMask SavedRegs = 1<<EBX | 1<<EDI | 1<<ESI
static const RegisterMask GpRegs = SavedRegs | 1<<EAX | 1<<ECX | 1<<EDX
static const RegisterMask XmmRegs = 1<<XMM0|1<<XMM1|1<<XMM2|1<<XMM3|1<<XMM4|1<<XMM5|1<<XMM6|1<<XMM7
static const RegisterMask x87Regs = 1<<FST0
static const RegisterMask FpRegs = x87Regs | XmmRegs
static const RegisterMask ScratchRegs = 1<<EAX | 1<<ECX | 1<<EDX | FpRegs
static const int NumSavedRegs = 3
static const RegisterMask AllowableFlagRegs = 1<<EAX |1<<ECX | 1<<EDX | 1<<EBX
const int NJ_LOG2_PAGE_SIZE = 12
const int NJ_MAX_REGISTERS = 6
const int NJ_MAX_STACK_ENTRY = 256
const int NJ_MAX_PARAMETERS = 1
const int NJ_ALIGN_STACK = 8
const int NJ_STACK_OFFSET = 8
const int NJ_MAX_CPOOL_OFFSET = 1024
const int NJ_CPOOL_SIZE = 16
static const RegisterMask SavedRegs = 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7
static const RegisterMask FpRegs = 0x0000
static const RegisterMask GpRegs = 0x003F
static const RegisterMask AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5

Typedef Documentation

typedef avmplus::List<Page*,avmplus::LIST_NonGCObjects> nanojit::AllocList
 

Definition at line 59 of file Fragmento.h.

typedef avmplus::GCSortedMap<const void*, uint32_t, avmplus::LIST_NonGCObjects> nanojit::BlockSortedMap
 

Definition at line 61 of file Fragmento.h.

typedef struct nanojit::_FragInfo nanojit::FragInfo
 

typedef struct nanojit::_FragInfo nanojit::FragInfo
 

typedef avmplus::SortedMap<LIns*,NIns*,avmplus::LIST_NonGCObjects> nanojit::InsMap
 

Definition at line 148 of file Assembler.h.

typedef LIns* nanojit::LInsp
 

Definition at line 435 of file LIR.h.

typedef unsigned short nanojit::NIns
 

Definition at line 62 of file NativeThumb.h.

typedef uint8_t nanojit::NIns
 

Definition at line 104 of file Nativei386.h.

typedef int nanojit::NIns
 

Definition at line 60 of file NativeARM.h.

typedef uint8_t nanojit::NIns
 

Definition at line 59 of file NativeAMD64.h.

typedef avmplus::List<NIns*, avmplus::LIST_NonGCObjects> nanojit::NInsList
 

Definition at line 147 of file Assembler.h.

typedef avmplus::SortedMap<NIns*,LIns*,avmplus::LIST_NonGCObjects> nanojit::NInsMap
 

Definition at line 149 of file Assembler.h.

typedef int nanojit::RegisterMask
 

Definition at line 96 of file NativeThumb.h.

typedef int nanojit::RegisterMask
 

Definition at line 148 of file Nativei386.h.

typedef int nanojit::RegisterMask
 

Definition at line 121 of file NativeARM.h.

typedef int nanojit::RegisterMask
 

Definition at line 109 of file NativeAMD64.h.

Enumeration Type Documentation

enum nanojit::AbiKind
 

Enumerator:
ABI_FASTCALL 
ABI_THISCALL 
ABI_STDCALL 
ABI_CDECL 

Definition at line 168 of file LIR.h.

00168                  {
00169         ABI_FASTCALL,
00170         ABI_THISCALL,
00171         ABI_STDCALL,
00172         ABI_CDECL
00173     };

enum nanojit::ArgSize
 

Enumerator:
ARGSIZE_NONE 
ARGSIZE_F 
ARGSIZE_LO 
ARGSIZE_Q 
_ARGSIZE_MASK_INT 
_ARGSIZE_MASK_ANY 

Definition at line 175 of file LIR.h.

00175                  {
00176         ARGSIZE_NONE = 0,
00177         ARGSIZE_F = 1,
00178         ARGSIZE_LO = 2,
00179         ARGSIZE_Q = 3,
00180         _ARGSIZE_MASK_INT = 2, 
00181         _ARGSIZE_MASK_ANY = 3
00182     };

enum nanojit::AssmError
 

Enumerator:
None 
OutOMem 
StackFull 
ResvFull 
RegionFull 
MaxLength 
MaxExit 
MaxXJump 
UnknownPrim 
UnknownBranch 

Definition at line 133 of file Assembler.h.

00134     {
00135          None = 0
00136         ,OutOMem
00137         ,StackFull
00138         ,ResvFull
00139         ,RegionFull
00140         ,MaxLength
00141         ,MaxExit
00142         ,MaxXJump
00143         ,UnknownPrim
00144         ,UnknownBranch
00145     };

enum nanojit::ConditionCode
 

Enumerator:
EQ 
NE 
CS 
CC 
MI 
PL 
VS 
VC 
HI 
LS 
GE 
LT 
GT 
LE 
AL 
NV 

Definition at line 99 of file NativeARM.h.

00100     {
00101         EQ = 0x0, // Equal
00102         NE = 0x1, // Not Equal
00103         CS = 0x2, // Carry Set (or HS)
00104         CC = 0x3, // Carry Clear (or LO)
00105         MI = 0x4, // MInus
00106         PL = 0x5, // PLus
00107         VS = 0x6, // oVerflow Set
00108         VC = 0x7, // oVerflow Clear
00109         HI = 0x8, // HIgher
00110         LS = 0x9, // Lower or Same
00111         GE = 0xA, // Greater or Equal
00112         LT = 0xB, // Less Than
00113         GT = 0xC, // Greater Than
00114         LE = 0xD, // Less or Equal
00115         AL = 0xE, // ALways
00116         NV = 0xF  // NeVer
00117     }

enum nanojit::LOpcode
 

Enumerator:
LIR64 
LIR_start 
LIR_nearskip 
LIR_skip 
LIR_neartramp 
LIR_tramp 
LIR_addp 
LIR_param 
LIR_st 
LIR_ld 
LIR_alloc 
LIR_sti 
LIR_ret 
LIR_live 
LIR_calli 
LIR_call 
LIR_loop 
LIR_x 
LIR_j 
LIR_jt 
LIR_jf 
LIR_label 
LIR_ji 
LIR_feq 
LIR_flt 
LIR_fgt 
LIR_fle 
LIR_fge 
LIR_cmov 
LIR_short 
LIR_int 
LIR_ldc 
LIR_2 
LIR_neg 
LIR_add 
LIR_sub 
LIR_mul 
LIR_callh 
LIR_and 
LIR_or 
LIR_xor 
LIR_not 
LIR_lsh 
LIR_rsh 
LIR_ush 
LIR_xt 
LIR_xf 
LIR_qlo 
LIR_qhi 
LIR_ldcb 
LIR_ov 
LIR_cs 
LIR_eq 
LIR_lt 
LIR_gt 
LIR_le 
LIR_ge 
LIR_ult 
LIR_ugt 
LIR_ule 
LIR_uge 
LIR_file 
LIR_line 
LIR_stq  64bit operations
LIR_stqi 
LIR_fret 
LIR_quad 
LIR_ldq 
LIR_ldqc 
LIR_fcall 
LIR_fcalli 
LIR_fneg 
LIR_fadd 
LIR_fsub 
LIR_fmul 
LIR_fdiv 
LIR_qjoin 
LIR_i2f 
LIR_u2f 

Definition at line 48 of file LIR.h.

00049     {
00050         // flags; upper bits reserved
00051         LIR64   = 0x40,         // result is double or quad
00052         
00053         // special operations (must be 0..N)
00054         LIR_start =     0,  
00055         LIR_nearskip =  1, // must be LIR_skip-1 and lsb=1
00056         LIR_skip =      2,
00057         LIR_neartramp = 3, // must be LIR_tramp-1 and lsb=1
00058         LIR_tramp =     4,
00059         
00060         // non-pure operations
00061         LIR_addp    = 9,
00062         LIR_param   = 10,
00063         LIR_st      = 11,
00064         LIR_ld      = 12,
00065         LIR_alloc   = 13, // alloca some stack space
00066         LIR_sti     = 14,
00067         LIR_ret     = 15,
00068         LIR_live    = 16, // extend live range of reference
00069         LIR_calli   = 17, // indirect call
00070         LIR_call    = 18, // direct call
00071             
00072         // guards
00073         LIR_loop    = 19, // loop fragment
00074         LIR_x       = 20, // exit always
00075 
00076         // branches
00077         LIR_j       = 21, // jump always
00078         LIR_jt      = 22, // jump true
00079         LIR_jf      = 23, // jump false
00080         LIR_label   = 24, // a jump target
00081         LIR_ji      = 25, // jump indirect
00082         
00083         // operators
00084         LIR_feq     = 26,
00085         LIR_flt     = 27,
00086         LIR_fgt     = 28,
00087         LIR_fle     = 29,
00088         LIR_fge     = 30,
00089         LIR_cmov    = 31, // conditional move (op1=cond, op2=cond(iftrue,iffalse))
00090         LIR_short   = 32,
00091         LIR_int     = 33,
00092         LIR_ldc     = 34, // non-volatile load
00093         LIR_2       = 35, // wraps a pair of refs
00094         LIR_neg     = 36,                   // [ 1 integer input / integer output ]
00095         LIR_add     = 37,                   // [ 2 operand integer intputs / integer output ]
00096         LIR_sub     = 38,
00097         LIR_mul     = 39,
00098         LIR_callh   = 40,
00099         LIR_and     = 41,
00100         LIR_or      = 42,
00101         LIR_xor     = 43,
00102         LIR_not     = 44,
00103         LIR_lsh     = 45,
00104         LIR_rsh     = 46,   // >>
00105         LIR_ush     = 47,   // >>>
00106         // conditional guards, op^1 to complement
00107         LIR_xt      = 48, // exit if true   0x30 0011 0000
00108         LIR_xf      = 49, // exit if false  0x31 0011 0001
00109         LIR_qlo     = 50,
00110         LIR_qhi     = 51,
00111         LIR_ldcb    = 52, // non-volatile 8-bit load
00112 
00113         LIR_ov      = 53,
00114         LIR_cs      = 54,
00115         LIR_eq      = 55,
00116         // relational operators.  op^1 to swap left/right, op^3 to complement.
00117         LIR_lt      = 56, // 0x38 0011 1000
00118         LIR_gt      = 57, // 0x39 0011 1001
00119         LIR_le      = 58, // 0x3A 0011 1010
00120         LIR_ge      = 59, // 0x3B 0011 1011
00121         LIR_ult     = 60, // 0x3C 0011 1100
00122         LIR_ugt     = 61, // 0x3D 0011 1101
00123         LIR_ule     = 62, // 0x3E 0011 1110
00124         LIR_uge     = 63, // 0x3F 0011 1111
00125 
00126         // non-64bit ops, but we're out of code space below 64
00127         LIR_file    = 1 | LIR64,
00128         LIR_line    = 2 | LIR64,
00129 
00133         LIR_stq     = LIR_st | LIR64,
00134         LIR_stqi    = LIR_sti | LIR64,
00135         LIR_fret    = LIR_ret | LIR64,
00136         LIR_quad    = LIR_int | LIR64,
00137         LIR_ldq     = LIR_ld    | LIR64,
00138         LIR_ldqc    = LIR_ldc   | LIR64,
00139 
00140         LIR_fcall   = LIR_call  | LIR64,
00141         LIR_fcalli  = LIR_calli | LIR64,
00142         LIR_fneg    = LIR_neg  | LIR64,
00143         LIR_fadd    = LIR_add  | LIR64,
00144         LIR_fsub    = LIR_sub  | LIR64,
00145         LIR_fmul    = LIR_mul  | LIR64,
00146         LIR_fdiv    = 40        | LIR64,
00147 
00148         LIR_qjoin   = 41 | LIR64,
00149         LIR_i2f     = 42 | LIR64,
00150         LIR_u2f     = 43 | LIR64
00151     };

enum nanojit::Register
 

Enumerator:
R0 
R0 
R1 
R1 
R2 
R2 
R3 
R3 
R4 
R4 
R5 
R5 
R6 
R6 
R7 
R7 
R8 
R8 
R8 
IP 
IP 
SP 
SP 
SP 
SP 
LR 
LR 
PC 
PC 
FP 
FP 
FP 
FP 
FRAME_PTR 
FRAME_PTR 
FirstReg 
FirstReg 
FirstReg 
FirstReg 
LastReg 
LastReg 
LastReg 
LastReg 
Scratch 
Scratch 
UnknownReg 
UnknownReg 
UnknownReg 
UnknownReg 

Definition at line 65 of file NativeThumb.h.

00066     {
00067         R0  = 0,
00068         R1  = 1,
00069         R2  = 2,
00070         R3  = 3,
00071         R4  = 4,
00072         R5  = 5,
00073         R6  = 6,
00074         R7  = 7,
00075         R8  = 8,
00076         //R9  = 9,
00077         //R10 = 10,
00078         //R11  = 11,
00079         IP  = 12,
00080         SP  = 13,
00081         LR  = 14,
00082         PC  = 15,
00083 
00084         FP = SP,
00085         
00086         // helpers
00087         FRAME_PTR = R7,
00088         
00089         FirstReg = 0,
00090         LastReg = 5,
00091         Scratch = 6,
00092         UnknownReg = 6
00093     }

enum nanojit::Register
 

Enumerator:
EAX 
ECX 
EDX 
EBX 
ESP 
ESP 
EBP 
ESI 
EDI 
SP 
SP 
SP 
SP 
FP 
FP 
FP 
FP 
XMM0 
XMM0 
XMM1 
XMM1 
XMM2 
XMM2 
XMM3 
XMM3 
XMM4 
XMM4 
XMM5 
XMM5 
XMM6 
XMM6 
XMM7 
XMM7 
FST0 
FST1 
FST2 
FST3 
FST4 
FST5 
FST6 
FST7 
FirstReg 
FirstReg 
FirstReg 
FirstReg 
LastReg 
LastReg 
LastReg 
LastReg 
UnknownReg 
UnknownReg 
UnknownReg 
UnknownReg 

Definition at line 107 of file Nativei386.h.

00108     {
00109         // general purpose 32bit regs
00110         EAX = 0, // return value, scratch
00111         ECX = 1, // this/arg0, scratch
00112         EDX = 2, // arg1, return-msw, scratch
00113         EBX = 3,
00114         ESP = 4, // stack pointer
00115         EBP = 5, // frame pointer
00116         ESI = 6,
00117         EDI = 7,
00118 
00119         SP = ESP, // alias SP to ESP for convenience
00120         FP = EBP, // alias FP to EBP for convenience
00121 
00122         // SSE regs come before X87 so we prefer them
00123         XMM0 = 8,
00124         XMM1 = 9,
00125         XMM2 = 10,
00126         XMM3 = 11,
00127         XMM4 = 12,
00128         XMM5 = 13,
00129         XMM6 = 14,
00130         XMM7 = 15,
00131 
00132         // X87 regs
00133         FST0 = 16,
00134         FST1 = 17,
00135         FST2 = 18,
00136         FST3 = 19,
00137         FST4 = 20,
00138         FST5 = 21,
00139         FST6 = 22,
00140         FST7 = 23,
00141 
00142         FirstReg = 0,
00143         LastReg = 23,
00144         UnknownReg = 24
00145     }

enum nanojit::Register
 

Enumerator:
R0 
R0 
R1 
R1 
R2 
R2 
R3 
R3 
R4 
R4 
R5 
R5 
R6 
R6 
R7 
R7 
R8 
R8 
R8 
R9 
R9 
R10 
R10 
IP 
IP 
SP 
SP 
SP 
SP 
LR 
LR 
PC 
PC 
FP 
FP 
FP 
FP 
F0 
FRAME_PTR 
FRAME_PTR 
ESP 
ESP 
FirstReg 
FirstReg 
FirstReg 
FirstReg 
LastReg 
LastReg 
LastReg 
LastReg 
Scratch 
Scratch 
UnknownReg 
UnknownReg 
UnknownReg 
UnknownReg 

Definition at line 63 of file NativeARM.h.

00064     {
00065         R0  = 0,
00066         R1  = 1,
00067         R2  = 2,
00068         R3  = 3,
00069         R4  = 4,
00070         R5  = 5,
00071         R6  = 6,
00072         R7  = 7,
00073         R8  = 8,
00074         R9  = 9,
00075         R10 = 10,
00076         //FP  =11,
00077         IP  = 12,
00078         SP  = 13,
00079         LR  = 14,
00080         PC  = 15,
00081 
00082         FP = 13,
00083         
00084         // Pseudo-register for floating point
00085         F0  = 0,
00086 
00087         // helpers
00088         FRAME_PTR = 11,
00089         ESP = 13,
00090         
00091         FirstReg = 0,
00092         LastReg = 10,
00093         Scratch = 12,
00094         UnknownReg = 11
00095     }

enum nanojit::Register
 

Enumerator:
RAX 
RCX 
RDX 
RBX 
RSP 
RBP 
RSI 
RDI 
SP 
SP 
SP 
SP 
FP 
FP 
FP 
FP 
R8 
R8 
R8 
R9 
R9 
R10 
R10 
R11 
R12 
R13 
R14 
R15 
XMM0 
XMM0 
XMM1 
XMM1 
XMM2 
XMM2 
XMM3 
XMM3 
XMM4 
XMM4 
XMM5 
XMM5 
XMM6 
XMM6 
XMM7 
XMM7 
XMM8 
XMM9 
XMM10 
XMM11 
XMM12 
XMM13 
XMM14 
XMM15 
FirstReg 
FirstReg 
FirstReg 
FirstReg 
LastReg 
LastReg 
LastReg 
LastReg 
UnknownReg 
UnknownReg 
UnknownReg 
UnknownReg 

Definition at line 62 of file NativeAMD64.h.

00063     {
00064         // general purpose 32bit regs
00065         RAX = 0, // return value, scratch
00066         RCX = 1, // this/arg0, scratch
00067         RDX = 2, // arg1, return-msw, scratch
00068         RBX = 3,
00069         RSP = 4, // stack pointer
00070         RBP = 5, // frame pointer
00071         RSI = 6,
00072         RDI = 7,
00073 
00074         SP = RSP, // alias SP to RSP for convenience
00075         FP = RBP, // alias FP to RBP for convenience
00076 
00077         R8 = 8,
00078         R9 = 9,
00079         R10 = 10,
00080         R11 = 11,
00081         R12 = 12,
00082         R13 = 13,
00083         R14 = 14,
00084         R15 = 15,
00085 
00086         XMM0 = 16,
00087         XMM1 = 17,
00088         XMM2 = 18,
00089         XMM3 = 19,
00090         XMM4 = 20,
00091         XMM5 = 21,
00092         XMM6 = 22,
00093         XMM7 = 23,
00094         XMM8 = 24,
00095         XMM9 = 25,
00096         XMM10 = 26,
00097         XMM11 = 27,
00098         XMM12 = 28,
00099         XMM13 = 29,
00100         XMM14 = 30,
00101         XMM15 = 31,
00102 
00103         FirstReg = 0,
00104         LastReg = 31,
00105         UnknownReg = 32
00106     }

enum nanojit::TraceKind
 

Enumerator:
LoopTrace 
BranchTrace 
MergeTrace 

Definition at line 144 of file Fragmento.h.

00144                    {
00145         LoopTrace,
00146         BranchTrace,
00147         MergeTrace
00148     };

Function Documentation

uint32_t nanojit::argwords (  uint32_t  argc  )  [inline]
 

Definition at line 161 of file LIR.h.

Referenced by nanojit::LIns::arg().

00161                                             {
00162         return (argc+3)>>2;
00163     }

LIns* FASTCALL nanojit::callArgN (  LInsp  i,
uint32_t  n
) 
 

void nanojit::compile (  Assembler *  assm,
Fragment *  frag
) 
 

Referenced by avmplus::NativeID::shell_toplevel_d2d_oaou_thunkc().

int32_t nanojit::disp (  Reservation *  r  )  [inline]
 

Definition at line 374 of file Assembler.h.

References nanojit::Reservation::arIndex, NJ_STACK_OFFSET, stack_direction, and STACK_GRANULARITY.

Referenced by axtam::IDispatchConsumer::call(), and nanojit::LirWriter::insStore().

00375     {
00376         return stack_direction((int32_t)STACK_GRANULARITY) * int32_t(r->arIndex) + NJ_STACK_OFFSET; 
00377     }

bool nanojit::isCall (  LOpcode  op  )  [inline]
 

Definition at line 215 of file LIR.h.

References LIR64, LIR_call, and LIR_calli.

Referenced by nanojit::LIns::isCall().

00215                                    {
00216         op = LOpcode(op & ~LIR64);
00217         return op == LIR_call || op == LIR_calli;
00218     }

bool FASTCALL nanojit::isCmp (  LOpcode  v  ) 
 

bool FASTCALL nanojit::isCond (  LOpcode  v  ) 
 

bool nanojit::isConst (  LOpcode  op  )  [inline]
 

Definition at line 225 of file LIR.h.

References LIR_short.

Referenced by nanojit::LIns::isconst().

00225                                     {
00226         return (op & ~1) == LIR_short;
00227     }

bool FASTCALL nanojit::isCse (  LOpcode  v  ) 
 

bool FASTCALL nanojit::isFloat (  LOpcode  v  ) 
 

bool nanojit::isGuard (  LOpcode  op  )  [inline]
 

Definition at line 211 of file LIR.h.

References LIR_loop, LIR_x, LIR_xf, and LIR_xt.

Referenced by nanojit::LIns::isGuard().

00211                                     {
00212         return op==LIR_x || op==LIR_xf || op==LIR_xt || op==LIR_loop;
00213     }

bool nanojit::isLoad (  LOpcode  op  )  [inline]
 

Definition at line 229 of file LIR.h.

References LIR_ld, LIR_ldc, LIR_ldq, and LIR_ldqc.

Referenced by nanojit::LIns::isLoad().

00229                                    {
00230         return op == LIR_ldq || op == LIR_ld || op == LIR_ldc || op == LIR_ldqc;
00231     }

bool nanojit::isRet (  LOpcode  c  )  [inline]
 

Definition at line 440 of file LIR.h.

References LIR64, and LIR_ret.

00440                                  {
00441         return (c & ~LIR64) == LIR_ret;
00442     }

bool nanojit::isStore (  LOpcode  op  )  [inline]
 

Definition at line 220 of file LIR.h.

References LIR64, LIR_st, and LIR_sti.

Referenced by nanojit::LIns::isStore().

00220                                     {
00221         op = LOpcode(op & ~LIR64);
00222         return op == LIR_st || op == LIR_sti;
00223     }

RegisterMask nanojit::rmask (  Register  r  )  [inline]
 

Definition at line 46 of file RegAlloc.h.

00047     {
00048         return 1 << r;
00049     }

nanojit::verbose_only (  extern const char *regNames;  []  ) 
 

Definition at line 138 of file NativeARM.h.

References DECLARE_PLATFORM_STATS, and nExtractPlatformFlags.

00165                         { NIns* _tins = _nIns; _nIns=_nExitIns; _nExitIns=_tins; \
00166                                 int* _nslot = _nSlot;\
00167                                 _nSlot = _nExitSlot;\
00168                                 _nExitSlot = _nslot;}
00169 
00170 
00171 #define IMM32(imm)  *(--_nIns) = (NIns)((imm));
00172 
00173 #define FUNCADDR(addr) ( ((int)addr) )  
00174 
00175 
00176 #define OP_IMM  (1<<25)
00177 
00178 #define COND_AL (0xE<<28)
00179 
00180 typedef enum
00181 {
00182     LSL_imm = 0, // LSL #c - Logical Shift Left
00183     LSL_reg = 1, // LSL Rc - Logical Shift Left
00184     LSR_imm = 2, // LSR #c - Logical Shift Right
00185     LSR_reg = 3, // LSR Rc - Logical Shift Right
00186     ASR_imm = 4, // ASR #c - Arithmetic Shift Right
00187     ASR_reg = 5, // ASR Rc - Arithmetic Shift Right
00188     ROR_imm = 6, // Rotate Right (c != 0)
00189     RRX     = 6, // Rotate Right one bit with extend (c == 0)
00190     ROR_reg = 7  // Rotate Right
00191 }

nanojit::verbose_only (  void printTracker(const char *s, avmplus::RegionTracker &trk, Assembler *assm);   ) 
 

Variable Documentation

const RegisterMask nanojit::AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 [static]
 

Definition at line 107 of file NativeThumb.h.

const RegisterMask nanojit::AllowableFlagRegs = 1<<EAX |1<<ECX | 1<<EDX | 1<<EBX [static]
 

Definition at line 158 of file Nativei386.h.

const RegisterMask nanojit::AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10 [static]
 

Definition at line 132 of file NativeARM.h.

const RegisterMask nanojit::AllowableFlagRegs = GpRegs [static]
 

Definition at line 121 of file NativeAMD64.h.

const RegisterMask nanojit::FpRegs = 0x0000 [static]
 

Definition at line 105 of file NativeThumb.h.

const RegisterMask nanojit::FpRegs = x87Regs | XmmRegs [static]
 

Definition at line 154 of file Nativei386.h.

const RegisterMask nanojit::FpRegs = 0x0000 [static]
 

Definition at line 130 of file NativeARM.h.

const RegisterMask nanojit::FpRegs = XmmRegs [static]
 

Definition at line 118 of file NativeAMD64.h.

const RegisterMask nanojit::GpRegs = 0x003F [static]
 

Definition at line 106 of file NativeThumb.h.

const RegisterMask nanojit::GpRegs = SavedRegs | 1<<EAX | 1<<ECX | 1<<EDX [static]
 

Definition at line 151 of file Nativei386.h.

const RegisterMask nanojit::GpRegs = 0x07FF [static]
 

Definition at line 131 of file NativeARM.h.

const RegisterMask nanojit::GpRegs = SavedRegs | TempRegs [static]
 

Definition at line 115 of file NativeAMD64.h.

LirBuffer* nanojit::lirbuf
 

Definition at line 847 of file LIR.h.

const int nanojit::NJ_ALIGN_STACK = 8
 

Definition at line 50 of file NativeThumb.h.

const int nanojit::NJ_ALIGN_STACK = 16
 

Definition at line 102 of file Nativei386.h.

const int nanojit::NJ_ALIGN_STACK = 16
 

Definition at line 57 of file NativeAMD64.h.

const int nanojit::NJ_CPOOL_SIZE = 16
 

Definition at line 55 of file NativeThumb.h.

const int nanojit::NJ_CPOOL_SIZE = 16
 

Definition at line 58 of file NativeARM.h.

const int nanojit::NJ_LOG2_PAGE_SIZE = 12
 

Definition at line 46 of file NativeThumb.h.

const int nanojit::NJ_LOG2_PAGE_SIZE = 12
 

Definition at line 92 of file Nativei386.h.

const int nanojit::NJ_LOG2_PAGE_SIZE = 12
 

Definition at line 46 of file NativeARM.h.

const int nanojit::NJ_LOG2_PAGE_SIZE = 12
 

Definition at line 46 of file NativeAMD64.h.

Referenced by nanojit::Fragmento::cacheUsedMax(), and nanojit::Fragmento::verbose_only().

const int nanojit::NJ_MAX_CPOOL_OFFSET = 1024
 

Definition at line 54 of file NativeThumb.h.

const int nanojit::NJ_MAX_CPOOL_OFFSET = 4096
 

Definition at line 57 of file NativeARM.h.

const int nanojit::NJ_MAX_PARAMETERS = 1
 

Definition at line 49 of file NativeThumb.h.

const int nanojit::NJ_MAX_REGISTERS = 6
 

Definition at line 47 of file NativeThumb.h.

const int nanojit::NJ_MAX_REGISTERS = 24
 

Definition at line 93 of file Nativei386.h.

const int nanojit::NJ_MAX_REGISTERS = 32
 

Definition at line 47 of file NativeAMD64.h.

const int nanojit::NJ_MAX_STACK_ENTRY = 256
 

Definition at line 48 of file NativeThumb.h.

const uint32_t nanojit::NJ_PAGE_SIZE = 1 << NJ_LOG2_PAGE_SIZE
 

Definition at line 61 of file Native.h.

Referenced by nanojit::LIns::page().

const int nanojit::NJ_STACK_OFFSET = 8
 

Definition at line 51 of file NativeThumb.h.

const int nanojit::NJ_STACK_OFFSET = 0
 

Definition at line 94 of file Nativei386.h.

const int nanojit::NJ_STACK_OFFSET = 0
 

Definition at line 48 of file NativeAMD64.h.

Referenced by disp().

const bool nanojit::NJ_UNLIMITED_GROWTH = true
 

Definition at line 51 of file NativeAMD64.h.

const int nanojit::NumSavedRegs = 3 [static]
 

Definition at line 156 of file Nativei386.h.

const uint8_t nanojit::operandCount[]
 

const RegisterMask nanojit::SavedRegs = 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 [static]
 

Definition at line 104 of file NativeThumb.h.

const RegisterMask nanojit::SavedRegs = 1<<EBX | 1<<EDI | 1<<ESI [static]
 

Definition at line 150 of file Nativei386.h.

const RegisterMask nanojit::SavedRegs = 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10 [static]
 

Definition at line 129 of file NativeARM.h.

const RegisterMask nanojit::SavedRegs = (1<<R13) | (1<<R14) | (1<<R15) [static]
 

Definition at line 112 of file NativeAMD64.h.

const RegisterMask nanojit::ScratchRegs = 1<<EAX | 1<<ECX | 1<<EDX | FpRegs [static]
 

Definition at line 155 of file Nativei386.h.

const RegisterMask nanojit::ScratchRegs = TempRegs | XmmRegs [static]
 

Definition at line 119 of file NativeAMD64.h.

nanojit::ShiftOperator
 

Definition at line 192 of file NativeARM.h.

const RegisterMask nanojit::TempRegs = (1<<RAX) | (1<<RCX) | (1<<RDX) | (1<<R8) | (1<<R9) | (1<<R10) | (1<<R11) | (1<<RDI) | (1<<RSI) [static]
 

Definition at line 114 of file NativeAMD64.h.

const RegisterMask nanojit::x87Regs = 1<<FST0 [static]
 

Definition at line 153 of file Nativei386.h.

const RegisterMask nanojit::XmmRegs = 1<<XMM0|1<<XMM1|1<<XMM2|1<<XMM3|1<<XMM4|1<<XMM5|1<<XMM6|1<<XMM7 [static]
 

Definition at line 152 of file Nativei386.h.

const RegisterMask nanojit::XmmRegs = (1<<XMM0) | (1<<XMM1) | (1<<XMM2) | (1<<XMM3) | (1<<XMM4) | (1<<XMM5) | (1<<XMM6) | (1<<XMM7) | (1<<XMM8) | (1<<XMM9) | (1<<XMM10) | (1<<XMM11) | (1<<XMM13) | (1<<XMM14) | (1<<XMM15) [static]
 

Definition at line 117 of file NativeAMD64.h.

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