avmplus::ArmAssembler

avmplus::ArmAssembler Class Reference

#include <ArmAssembler.h>

List of all members.

Public Types

typedef uint32 MDInstruction
enum  Register {
  R0 = 0, R1 = 1, R2 = 2, R3 = 3,
  R4 = 4, R5 = 5, R6 = 6, R7 = 7,
  R8 = 8, R9 = 9, R10 = 10, FP = 11,
  IP = 12, SP = 13, LR = 14, PC = 15,
  F0 = 0, Unknown = -1
}
enum  RegisterMask {
  R0_mask = (1<<0), R1_mask = (1<<1), R2_mask = (1<<2), R3_mask = (1<<3),
  R4_mask = (1<<4), R5_mask = (1<<5), R6_mask = (1<<6), R7_mask = (1<<7),
  R8_mask = (1<<8), R9_mask = (1<<9), R10_mask = (1<<10), FP_mask = (1<<11),
  IP_mask = (1<<12), SP_mask = (1<<13), LR_mask = (1<<14), PC_mask = (1<<15)
}
enum  ConditionCode {
  EQ = 0x0, NE = 0x1, CS = 0x2, CC = 0x3,
  MI = 0x4, PL = 0x5, VS = 0x6, VC = 0x7,
  HI = 0x8, LS = 0x9, GE = 0xA, LT = 0xB,
  GT = 0xC, LE = 0xD, AL = 0xE, NV = 0xF
}
enum  Operator {
  AND_op = 0x0, EOR_op = 0x1, SUB_op = 0x2, RSB_op = 0x3,
  ADD_op = 0x4, ADC_op = 0x5, SBC_op = 0x6, RSC_op = 0x7,
  TST_op = 0x8, TEQ_op = 0x9, CMP_op = 0xA, CMN_op = 0xB,
  ORR_op = 0xC, MOV_op = 0xD, BIC_op = 0xE, MVN_op = 0xF
}
enum  ShiftOperator {
  LSL_imm = 0, LSL_reg = 1, LSR_imm = 2, LSR_reg = 3,
  ASR_imm = 4, ASR_reg = 5, ROR_imm = 6, RRX = 6,
  ROR_reg = 7
}

Public Member Functions

 ArmAssembler ()
void SET_CONDITION_CODE (ConditionCode conditionCode)
void IMM32 (int value)
void MOV (Register dst, Register src)
void STMFD_bang (Register dst, int mask)
void SUB_imm8 (Register dst, Register src, int imm8)
void RSB_imm8 (Register dst, Register src, int imm8)
void B (int offset24)
void BL (int offset24)
void LDR (Register dst, int offset, Register base)
void BIC_imm8 (Register dst, Register src, int imm8)
void MOV_imm8 (Register dst, int imm8)
void MOV_imm16 (Register dst, int imm16)
void CMP_imm8 (Register src, int imm8)
void ADD (Register dst, Register src1, Register src2)
void SUB (Register dst, Register src1, Register src2)
void AND (Register dst, Register src1, Register src2)
void ORR (Register dst, Register src1, Register src2)
void EOR (Register dst, Register src1, Register src2)
void MUL (Register dst, Register src1, Register src2)
void CMP (Register Rn, Register Rm)
void LSL (Register dst, Register src, Register rShift)
void LSR (Register dst, Register src, Register rShift)
void ASR (Register dst, Register src, Register rShift)
void LSL_i (Register dst, Register src, int iShift)
void LSR_i (Register dst, Register src, int iShift)
void ASR_i (Register dst, Register src, int iShift)
void STR (Register src, int offset, Register base)
void ADD_imm8 (Register dst, Register src, int imm8)
void ADD_imm8_hi (Register dst, Register src, int imm8)
void ADD_imm16 (Register dst, Register src, int imm16)
void AND_imm8 (Register dst, Register src, int imm8)
void ORR_imm8 (Register dst, Register src, int imm8)
void EOR_imm8 (Register dst, Register src, int imm8)
void LDMFD (Register src, int mask)
void LDMFD_bang (Register src, int mask)
void MOV_imm32 (Register dst, int imm32)
void flushDataCache (void *start, int len)

Public Attributes

MDInstruction * mip
MDInstruction * mipStart
int mInstructionCount
ConditionCode conditionCode
PrintWriter * console
MDInstruction * immediatePool
int immediatePoolCount

Static Public Attributes

static const int kImmediatePoolMax = 16
static const char *const regNames []
static const char *const conditionCodes []

Detailed Description

Definition at line 44 of file ArmAssembler.h.

Member Typedef Documentation

typedef uint32 avmplus::ArmAssembler::MDInstruction
 

Definition at line 157 of file ArmAssembler.h.

Member Enumeration Documentation

enum avmplus::ArmAssembler::ConditionCode
 

Enumerator:
EQ 
NE 
CS 
CC 
MI 
PL 
VS 
VC 
HI 
LS 
GE 
LT 
GT 
LE 
AL 
NV 

Definition at line 97 of file ArmAssembler.h.

00098         {
00099             EQ = 0x0, // Equal
00100             NE = 0x1, // Not Equal
00101             CS = 0x2, // Carry Set (or HS)
00102             CC = 0x3, // Carry Clear (or LO)
00103             MI = 0x4, // MInus
00104             PL = 0x5, // PLus
00105             VS = 0x6, // oVerflow Set
00106             VC = 0x7, // oVerflow Clear
00107             HI = 0x8, // HIgher
00108             LS = 0x9, // Lower or Same
00109             GE = 0xA, // Greater or Equal
00110             LT = 0xB, // Less Than
00111             GT = 0xC, // Greater Than
00112             LE = 0xD, // Less or Equal
00113             AL = 0xE, // ALways
00114             NV = 0xF  // NeVer
00115         }

enum avmplus::ArmAssembler::Operator
 

Enumerator:
AND_op 
EOR_op 
SUB_op 
RSB_op 
ADD_op 
ADC_op 
SBC_op 
RSC_op 
TST_op 
TEQ_op 
CMP_op 
CMN_op 
ORR_op 
MOV_op 
BIC_op 
MVN_op 

Definition at line 121 of file ArmAssembler.h.

00122         {
00123             AND_op = 0x0, // Boolean And                 Rd = Rn AND Op2
00124             EOR_op = 0x1, // Boolean Eor                 Rd = Rn EOR Op2
00125             SUB_op = 0x2, // Subtract                    Rd = Rn - Op2
00126             RSB_op = 0x3, // Reverse Subtract            Rd = Op2 - Rn
00127             ADD_op = 0x4, // Addition                    Rd = Rn + Op2
00128             ADC_op = 0x5, // Add with Carry              Rd = Rn + Op2 + C
00129             SBC_op = 0x6, // Subtract with Carry         Rd = Rn - Op2 - (1-C)
00130             RSC_op = 0x7, // Reverse Subtract with Carry Rd - Op2 - Rn - (1-C)
00131             TST_op = 0x8, // Test bit                    Rn AND Op2
00132             TEQ_op = 0x9, // Test equality               Rn EOR Op2
00133             CMP_op = 0xA, // Compare                     Rn - Op2
00134             CMN_op = 0xB, // Compare Negative            Rn + Op2
00135             ORR_op = 0xC, // Boolean Or                  Rd = Rn OR Op2
00136             MOV_op = 0xD, // Move value                  Rd = Op2
00137             BIC_op = 0xE, // Bit Clear                   Rd = Rn AND NOT Op2
00138             MVN_op = 0xF  // Move Not                    Rd = NOT Op2
00139         }

enum avmplus::ArmAssembler::Register
 

Enumerator:
R0 
R1 
R2 
R3 
R4 
R5 
R6 
R7 
R8 
R9 
R10 
FP 
IP 
SP 
LR 
PC 
F0 
Unknown 

Definition at line 48 of file ArmAssembler.h.

00049         {
00050             R0  = 0,
00051             R1  = 1,
00052             R2  = 2,
00053             R3  = 3,
00054             R4  = 4,
00055             R5  = 5,
00056             R6  = 6,
00057             R7  = 7,
00058             R8  = 8,
00059             R9  = 9,
00060             R10 = 10,
00061             FP  = 11,
00062             IP  = 12,
00063             SP  = 13,
00064             LR  = 14,
00065             PC  = 15,
00066 
00067             // Pseudo-register for floating point
00068             F0  = 0,
00069             
00070             Unknown = -1
00071         }

enum avmplus::ArmAssembler::RegisterMask
 

Enumerator:
R0_mask 
R1_mask 
R2_mask 
R3_mask 
R4_mask 
R5_mask 
R6_mask 
R7_mask 
R8_mask 
R9_mask 
R10_mask 
FP_mask 
IP_mask 
SP_mask 
LR_mask 
PC_mask 

Definition at line 75 of file ArmAssembler.h.

00076         {
00077             R0_mask  = (1<<0),
00078             R1_mask  = (1<<1),
00079             R2_mask  = (1<<2),
00080             R3_mask  = (1<<3),
00081             R4_mask  = (1<<4),
00082             R5_mask  = (1<<5),
00083             R6_mask  = (1<<6),
00084             R7_mask  = (1<<7),
00085             R8_mask  = (1<<8),
00086             R9_mask  = (1<<9),
00087             R10_mask = (1<<10),
00088             FP_mask  = (1<<11),
00089             IP_mask  = (1<<12),
00090             SP_mask  = (1<<13),
00091             LR_mask  = (1<<14),
00092             PC_mask  = (1<<15)
00093         }

enum avmplus::ArmAssembler::ShiftOperator
 

Enumerator:
LSL_imm 
LSL_reg 
LSR_imm 
LSR_reg 
ASR_imm 
ASR_reg 
ROR_imm 
RRX 
ROR_reg 

Definition at line 143 of file ArmAssembler.h.

00144         {
00145             LSL_imm = 0, // LSL #c - Logical Shift Left
00146             LSL_reg = 1, // LSL Rc - Logical Shift Left
00147             LSR_imm = 2, // LSR #c - Logical Shift Right
00148             LSR_reg = 3, // LSR Rc - Logical Shift Right
00149             ASR_imm = 4, // ASR #c - Arithmetic Shift Right
00150             ASR_reg = 5, // ASR Rc - Arithmetic Shift Right
00151             ROR_imm = 6, // Rotate Right (c != 0)
00152             RRX     = 6, // Rotate Right one bit with extend (c == 0)
00153             ROR_reg = 7  // Rotate Right
00154         }

Constructor & Destructor Documentation

avmplus::ArmAssembler::ArmAssembler (   ) 
 

Member Function Documentation

void avmplus::ArmAssembler::ADD (  Register  dst,
Register  src1,
Register  src2
) 
 

void avmplus::ArmAssembler::ADD_imm16 (  Register  dst,
Register  src,
int  imm16
) 
 

void avmplus::ArmAssembler::ADD_imm8 (  Register  dst,
Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::ADD_imm8_hi (  Register  dst,
Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::AND (  Register  dst,
Register  src1,
Register  src2
) 
 

void avmplus::ArmAssembler::AND_imm8 (  Register  dst,
Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::ASR (  Register  dst,
Register  src,
Register  rShift
) 
 

void avmplus::ArmAssembler::ASR_i (  Register  dst,
Register  src,
int  iShift
) 
 

void avmplus::ArmAssembler::B (  int  offset24  ) 
 

void avmplus::ArmAssembler::BIC_imm8 (  Register  dst,
Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::BL (  int  offset24  ) 
 

void avmplus::ArmAssembler::CMP (  Register  Rn,
Register  Rm
) 
 

void avmplus::ArmAssembler::CMP_imm8 (  Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::EOR (  Register  dst,
Register  src1,
Register  src2
) 
 

void avmplus::ArmAssembler::EOR_imm8 (  Register  dst,
Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::flushDataCache (  void *  start,
int  len
) 
 

void avmplus::ArmAssembler::IMM32 (  int  value  ) 
 

void avmplus::ArmAssembler::LDMFD (  Register  src,
int  mask
) 
 

void avmplus::ArmAssembler::LDMFD_bang (  Register  src,
int  mask
) 
 

void avmplus::ArmAssembler::LDR (  Register  dst,
int  offset,
Register  base
) 
 

void avmplus::ArmAssembler::LSL (  Register  dst,
Register  src,
Register  rShift
) 
 

void avmplus::ArmAssembler::LSL_i (  Register  dst,
Register  src,
int  iShift
) 
 

void avmplus::ArmAssembler::LSR (  Register  dst,
Register  src,
Register  rShift
) 
 

void avmplus::ArmAssembler::LSR_i (  Register  dst,
Register  src,
int  iShift
) 
 

void avmplus::ArmAssembler::MOV (  Register  dst,
Register  src
) 
 

void avmplus::ArmAssembler::MOV_imm16 (  Register  dst,
int  imm16
) 
 

void avmplus::ArmAssembler::MOV_imm32 (  Register  dst,
int  imm32
) 
 

void avmplus::ArmAssembler::MOV_imm8 (  Register  dst,
int  imm8
) 
 

void avmplus::ArmAssembler::MUL (  Register  dst,
Register  src1,
Register  src2
) 
 

void avmplus::ArmAssembler::ORR (  Register  dst,
Register  src1,
Register  src2
) 
 

void avmplus::ArmAssembler::ORR_imm8 (  Register  dst,
Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::RSB_imm8 (  Register  dst,
Register  src,
int  imm8
) 
 

void avmplus::ArmAssembler::SET_CONDITION_CODE (  ConditionCode  conditionCode  ) 
 

void avmplus::ArmAssembler::STMFD_bang (  Register  dst,
int  mask
) 
 

void avmplus::ArmAssembler::STR (  Register  src,
int  offset,
Register  base
) 
 

void avmplus::ArmAssembler::SUB (  Register  dst,
Register  src1,
Register  src2
) 
 

void avmplus::ArmAssembler::SUB_imm8 (  Register  dst,
Register  src,
int  imm8
) 
 

Member Data Documentation

ConditionCode avmplus::ArmAssembler::conditionCode
 

Definition at line 166 of file ArmAssembler.h.

const char* const avmplus::ArmAssembler::conditionCodes[] [static]
 

Definition at line 225 of file ArmAssembler.h.

PrintWriter* avmplus::ArmAssembler::console
 

Definition at line 216 of file ArmAssembler.h.

MDInstruction* avmplus::ArmAssembler::immediatePool
 

Definition at line 219 of file ArmAssembler.h.

int avmplus::ArmAssembler::immediatePoolCount
 

Definition at line 220 of file ArmAssembler.h.

const int avmplus::ArmAssembler::kImmediatePoolMax = 16 [static]
 

Definition at line 221 of file ArmAssembler.h.

int avmplus::ArmAssembler::mInstructionCount
 

Definition at line 163 of file ArmAssembler.h.

MDInstruction* avmplus::ArmAssembler::mip
 

Definition at line 160 of file ArmAssembler.h.

MDInstruction* avmplus::ArmAssembler::mipStart
 

Definition at line 161 of file ArmAssembler.h.

const char* const avmplus::ArmAssembler::regNames[] [static]
 

Definition at line 223 of file ArmAssembler.h.

The documentation for this class was generated from the following file:
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